Sub-1nm chips have crossed an extraordinary research milestone. IBM recently demonstrated technology for a 0.7-nanometer, or 7-angstrom, process node that could place nearly 100 billion transistors on a chip approximately the size of a fingernail.
The announcement pushes semiconductor development below the familiar nanometer range and into terminology normally used to describe atoms, chemical bonds and crystal structures. One nanometer equals 10 angstroms, while many distances between atoms inside solid materials are measured in only a few angstroms.
That does not mean IBM has created complete transistors measuring exactly 0.7 nanometers from one side to the other. Modern process names such as 3nm, 2nm and 0.7nm identify generations of manufacturing technology rather than one literal measurement shared by every feature.
The achievement is nonetheless significant. Engineers are now building functional transistor structures whose critical layers, channels and interfaces are approaching dimensions where individual atoms can affect electrical behavior.
Sub-1nm Chips Do Not Have 0.7nm Transistors
The naming system used by chipmakers once corresponded more closely with a physical transistor measurement. As designs became more complex, the node number evolved into a label representing improvements in density, performance and energy consumption.
A modern 2nm processor does not contain transistors in which every gate, wire and channel measures two nanometers. Some features are larger, while certain layers may already be thinner.
IBM describes its new technology as a 0.7nm node because it represents a manufacturing generation beyond 2nm and future angstrom-class processes. The designation communicates density and scaling progress rather than providing a ruler for the entire transistor.
The phrase “a few atoms wide” therefore requires context. Some materials inside advanced chips can be only several atomic layers thick. A complete transistor still consists of a channel, gate material, insulation, source and drain regions, electrical contacts and surrounding interconnects.
At these dimensions, removing or misplacing a small number of atoms can change how current flows. Manufacturing consistency becomes as consequential as the original transistor design.
IBM Builds Transistors Upward
IBM reached the sub-1nm milestone with a new architecture called nanostack.
Current leading-edge processors are moving toward gate-all-around nanosheet transistors. These designs replace the vertical fins used by FinFET processors with thin horizontal sheets surrounded by the transistor gate.
Wrapping the gate around the channel improves control over current. That control is needed because electricity becomes harder to contain as the distance between transistor regions decreases.
Nanostack adds another dimension by vertically stacking and staggering transistor layers. Instead of relying exclusively on placing smaller structures beside one another, IBM uses the space above the original layer.
The architecture allows different channel materials to be selected for different parts of the stack. Engineers can optimize one transistor layer for higher performance and another for lower energy consumption.
IBM also demonstrated working CMOS inverter operation, ultra-thin dielectric bonding and improvements to SRAM density. SRAM forms the high-speed cache placed close to processor cores, and it has become increasingly resistant to the shrink rates achieved by logic transistors.
The research indicates a possible route to 40% SRAM scaling, which could help future processors place more cache near CPU, GPU and AI accelerators.
Vertical Design Replaces Simple Shrinking
The industry can no longer depend on reducing every two-dimensional feature at the pace associated with earlier versions of Moore’s Law.
Planar transistors were replaced by FinFETs when flat channels became difficult to control. FinFETs are now giving way to gate-all-around nanosheets, while future designs may use forksheets and complementary field-effect transistors.
CFET technology places n-type and p-type transistor channels on top of one another. Conventional designs arrange those complementary devices side by side, consuming valuable surface area.
Stacking them vertically can reduce the space required for a standard logic cell without demanding that every individual feature shrink at the same rate.
The process is extremely difficult. Manufacturers must build and connect multiple transistor levels while preventing later production steps from damaging structures created earlier.
Heat is another constraint. Each new layer must be processed within a limited temperature range, and densely stacked transistors can concentrate thermal energy inside the chip.
The sub-1nm era will therefore be defined by architecture, materials and packaging as much as lithographic resolution.
Silicon Is Approaching Its Practical Limits
Silicon remains the foundation of modern processors, but extremely thin silicon channels lose some of their ability to carry electrical charge efficiently.
Researchers are studying two-dimensional semiconductors such as molybdenum disulfide and tungsten diselenide. These materials can form stable crystalline layers approximately 0.7nm thick.
Their atomic structure may allow current to remain controlled inside channels thinner than practical silicon alternatives. That property makes them candidates for future CFET and gate-all-around designs.
Industrial adoption remains distant. Manufacturers need methods for depositing defect-free material across 300-millimeter wafers, creating low-resistance contacts and producing consistent behavior across billions of transistors.
Traditional methods of adding impurities to silicon can also damage atomically thin materials. Researchers must develop new approaches for controlling their electrical characteristics without disrupting the channel.
A laboratory transistor can demonstrate exceptional performance while occupying a tiny test area. A commercial processor must repeat that performance billions of times with acceptable yields and years of reliability.
Lithography Must Become More Precise
Creating atomic-scale structures also requires improved lithography.
Extreme ultraviolet systems use light with a wavelength of 13.5nm to print circuit patterns onto silicon wafers. The wavelength is much larger than some finished chip features, forcing manufacturers to rely on optics, computational corrections and multiple processing steps.
High numerical aperture EUV increases the resolution available for future nodes. The machines use redesigned mirrors and a larger optical aperture to project finer patterns with fewer exposures.
The equipment is enormous despite producing microscopic structures. Intel described its first commercial High-NA EUV system as weighing 165 tons, illustrating the contrast between the scale of the factory machinery and the features it creates.
Lithography is only one part of the process. Atomic-scale chips also require deposition, etching, polishing and measurement systems capable of controlling layers with minimal variation.
A slightly uneven film or rough edge can represent a large percentage of a channel only a few atoms thick.
The First Products Remain Years Away
IBM says nanostack technology could reach its earliest production use within approximately five years. That target places potential adoption around 2031, and it does not guarantee immediate availability in consumer processors.
TSMC, which manufactures Apple-designed chips, is currently moving through nanosheet-based technologies planned before sub-1nm production. Its A14 process is scheduled for 2028, followed by A13 in 2029.
Those names also use angstrom-era branding without describing literal 1.4nm or 1.3nm transistor dimensions.
Future iPhone, iPad and Mac processors could eventually benefit from sub-1nm research through higher transistor density, larger caches and reduced energy consumption. The greatest mobile advantage may not be raw speed.
A processor able to complete the same work with substantially less energy could extend battery life, reduce heat and support more local AI processing without increasing device thickness.
The first commercial nanostack chips are more likely to appear in servers, AI accelerators or specialized high-performance systems where manufacturers can accept greater cost. Mobile versions would follow only after production yields improve and the technology can meet the strict power and reliability requirements of devices carried throughout the day.
